The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2012

Filed:

Jan. 22, 2007
Applicant:

Sebastien Nuttinck, Heverlee, BE;

Inventor:

Sebastien Nuttinck, Heverlee, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device () comprising a protrusion or fin structure with a plurality of stacked semiconductor regions (), in which a second semiconductor region () is separated from a first semiconductor region () by an isolation region (). A gate isolation layer () extends at least over the sidewalls of the protrusion () and a gate electrode extends over the gate isolation layer (). The gate electrode comprises a plurality of gate regions () wherein each gate region () extends over another semiconductor region (). In this way each gate region () influences the conduction channel of another semiconductor region () and hence adds another degree of freedom with which the performance of the SF-MOS device () can be optimized. The invention further provides a method of manufacturing the SF-MOS device () according to the invention.


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