The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2012
Filed:
Jul. 10, 2009
An-thung Cho, Hsin-Chu, TW;
Chia-tien Peng, Hsin-Chu, TW;
Chih-wei Chao, Hsin-Chu, TW;
Wan-yi Liu, Hsin-Chu, TW;
Chia-kai Chen, Hsin-Chu, TW;
Chun-hsiun Chen, Hsin-Chu, TW;
Wei-ming Huang, Hsin-Chu, TW;
An-Thung Cho, Hsin-Chu, TW;
Chia-Tien Peng, Hsin-Chu, TW;
Chih-Wei Chao, Hsin-Chu, TW;
Wan-Yi Liu, Hsin-Chu, TW;
Chia-Kai Chen, Hsin-Chu, TW;
Chun-Hsiun Chen, Hsin-Chu, TW;
Wei-Ming Huang, Hsin-Chu, TW;
Au Optronics Corp., Hsin-Chu, TW;
Abstract
A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer is formed on the semiconductor layer. After that, a plurality of silicon nanocrystals is formed in the Si-rich dielectric layer by a laser annealing process to form a charge-storing dielectric layer. Last, a gate electrode is formed on the charge-storing dielectric layer.