The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2012
Filed:
Jul. 13, 2009
Stefan Schwantes, Heilbronn, DE;
Volker Dudek, Brackenheim, DE;
Michael Graf, Leutenbach, DE;
Alan Renninger, San Jose, CA (US);
James Shen, Colorado Springs, CO (US);
Stefan Schwantes, Heilbronn, DE;
Volker Dudek, Brackenheim, DE;
Michael Graf, Leutenbach, DE;
Alan Renninger, San Jose, CA (US);
James Shen, Colorado Springs, CO (US);
Atmel Corporation, San Jose, CA (US);
Abstract
A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.