The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2012

Filed:

Nov. 21, 2008
Applicants:

Etsuko Nishimura, Hitachiota, JP;

Masatoshi Wakagi, Hitachinaka, JP;

Kenichi Onisawa, Hitachinaka, JP;

Mieko Matsumura, Kokubunji, JP;

Inventors:

Etsuko Nishimura, Hitachiota, JP;

Masatoshi Wakagi, Hitachinaka, JP;

Kenichi Onisawa, Hitachinaka, JP;

Mieko Matsumura, Kokubunji, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 35/24 (2006.01); H01L 51/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Each TFT for driving each of a plurality of pixels arranged in a matrix-like configuration is configured using a stagger-type polycrystalline-Si TFT. A gate electrode, which is composed of a high-heat-resistant material capable of resisting high temperature at the time of polycrystalline-Si film formation, is disposed at a lower layer as compared with the polycrystalline-Si layer that forms a channel of each TFT. A gate line, which is composed of a low-resistance material, is disposed at an upper layer as compared with the polycrystalline-Si layer. The gate electrode and the gate line are connected to each other via a through-hole bored in a gate insulation film. Respective configuration components of each organic electro-luminescent element are partially co-used at the time of the line formation, thereby suppressing an increase in the steps, processes, and configuration components.


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