The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2012
Filed:
May. 13, 2008
Martin Joseph Crippen, Apex, NC (US);
Brian Michael Kerrigan, Cary, NC (US);
Tony Carl Sass, Fuquay Varina, NC (US);
Martin Joseph Crippen, Apex, NC (US);
Brian Michael Kerrigan, Cary, NC (US);
Tony Carl Sass, Fuquay Varina, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A reduced insertion force mezzanine connector is used to couple first and second circuit boards. In one embodiment a connector frame has a first end disposed against the first circuit board and defining a first wall, and an opposing second end disposed against the second circuit board and defining a second wall generally parallel with the first wall. A plurality of wafers are disposed. Each wafer has a first edge in sliding contact with the first wall and an opposing second edge in sliding contact with the second wall. A plurality of electrically conducting pathways extend along each wafer from the first edge to the second edge. A wafer guide structure defines a plurality of wafer-support aisles on the first and second walls for receiving the edges of the wafers to constrain the wafers with a fixed spacing and generally parallel alignment. A plurality of terminals are biased to protrude laterally into each wafer support aisle, and are spaced along the wafer support aisle such that each wafer is movable within the respective wafer support aisle between a first position, wherein each electrically conducting pathway is disposed between adjacent terminals, to a second position, wherein each electrically conducting pathway is in electrical contact with a terminal on the first wall and an associated terminal on the second wall.