The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2012
Filed:
Oct. 01, 2008
Pradip Bose, Yorktown Heights, NY (US);
Prabhakar N. Kudva, Warwick, NY (US);
Jude A. Rivers, Cortlandt Manor, NY (US);
Pia N. Sanda, Slingerlands, NY (US);
John-david Wellman, Hopewell Junction, NY (US);
Pradip Bose, Yorktown Heights, NY (US);
Prabhakar N. Kudva, Warwick, NY (US);
Jude A. Rivers, Cortlandt Manor, NY (US);
Pia N. Sanda, Slingerlands, NY (US);
John-David Wellman, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.