The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2012

Filed:

Aug. 16, 2010
Applicants:

Hideyuki Noda, Hyogo, JP;

Kazunori Saitoh, Hyogo, JP;

Kazutami Arimoto, Hyogo, JP;

Katsumi Dosaka, Hyogo, JP;

Inventors:

Hideyuki Noda, Hyogo, JP;

Kazunori Saitoh, Hyogo, JP;

Kazutami Arimoto, Hyogo, JP;

Katsumi Dosaka, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.


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