The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2012

Filed:

Oct. 30, 2007
Applicants:

Dipankar Bhattacharya, Macungie, PA (US);

Makeshwar Kothandaraman, Whitehall, PA (US);

John C. Kriz, Palmerton, PA (US);

Bernard L. Morris, Emmaus, PA (US);

Yehuda Smooha, Allentown, PA (US);

Inventors:

Dipankar Bhattacharya, Macungie, PA (US);

Makeshwar Kothandaraman, Whitehall, PA (US);

John C. Kriz, Palmerton, PA (US);

Bernard L. Morris, Emmaus, PA (US);

Yehuda Smooha, Allentown, PA (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 3/22 (2006.01); H02H 3/20 (2006.01); H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.


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