The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2012

Filed:

Jun. 27, 2008
Applicants:

Jong Hae Kim, Gyeonggi-do, KR;

Jong Sun Kim, Gyeonggi-do, KR;

Dong Seong OH, Incheon, KR;

Don Sik Kim, Gyeonggi-do, KR;

Jae Sun Won, Gyeonggi-do, KR;

Jin Wok Kim, Seoul, KR;

Inventors:

Jong Hae Kim, Gyeonggi-do, KR;

Jong Sun Kim, Gyeonggi-do, KR;

Dong Seong Oh, Incheon, KR;

Don Sik Kim, Gyeonggi-do, KR;

Jae Sun Won, Gyeonggi-do, KR;

Jin Wok Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05B 37/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

In accordance with the present invention, the SMPS circuit for PDP includes first and second transformers inducing voltages supplied to primary sides to secondary sides; a plurality of DC/DC converters connected to secondary sides of the first and second transformers and supplying voltages of different sizes; a clamp circuit connected to the secondary side of the first transformer and outputting an address voltage of a predetermined size by receiving a voltage supplied from the first transformer; and a linear regulator unit connected to the DC/DC converter for supplying a low voltage among the DC/DC converters connected to the secondary side of the first transformer and outputting a gate voltage of a predetermined size by receiving the low voltage supplied from the DC/DC converter.


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