The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2011
Filed:
Apr. 09, 2008
Wilhelm Haller, Remshalden, DE;
Rolf Sautter, Bondorf, DE;
Christoph Wandel, Weil im Schoenbuch, DE;
Ulrich Weiss, Holzgerlingen, DE;
Wilhelm Haller, Remshalden, DE;
Rolf Sautter, Bondorf, DE;
Christoph Wandel, Weil im Schoenbuch, DE;
Ulrich Weiss, Holzgerlingen, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input () to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.