The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2011

Filed:

Aug. 25, 2009
Applicants:

Hajime Watakabe, Fukaya, JP;

Masato Hiramatsu, Tokyo, JP;

Toshiya Kiyota, Saitama, JP;

Mikio Murata, Kumagaya, JP;

Masaki Kado, Saitama, JP;

Arichika Ishida, Okegawa, JP;

Yoshiaki Nakazaki, Saitama, JP;

Inventors:

Hajime Watakabe, Fukaya, JP;

Masato Hiramatsu, Tokyo, JP;

Toshiya Kiyota, Saitama, JP;

Mikio Murata, Kumagaya, JP;

Masaki Kado, Saitama, JP;

Arichika Ishida, Okegawa, JP;

Yoshiaki Nakazaki, Saitama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structure of a plurality of thin film transistors wherein a peripheral circuit on a glass substrate of a liquid crystal display panel; and each of polycrystalline silicon thin filmof the thin film transistor is formed on the glass substrate; and each of gate electrodeis formed on a gate insulation layer, and each of the gate electrodeis overhead corresponding to the polycrystalline silicon thin filmfor a channel; wherein the gate electrodeis comprised a pair of projection partA and a gate-channelB; and wherein the pair of projection partA is formed the both sides of the gate-channelB in which the side is for along the channel-direction, and wherein the pair of projection partA is enlarged for across the channel-direction.


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