The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2011
Filed:
Dec. 21, 2006
Jonathon Stiff, Moscow, ID (US);
Jonathon Stiff, Moscow, ID (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A differential-to-single ended converter circuit can include a latching circuit having first and second latch field effect transistors (FETs) with drains and gates cross-coupled between a first latch node and a second latch node. The source-drain paths of the first and second latch FETs are coupled to a first reference potential node via separate current paths. A sense circuit can include a first sense FET having a source-drain path coupled between the first sense node and the first reference potential node, and a gate coupled to a first input node. A second sense FET has a source-drain path coupled between the second sense node and the first reference potential node, and a gate coupled to a second input node. An output circuit can have a first output FET with a source-drain path coupled between a first output supply node and an output signal node, and a gate coupled to the first latch node, and a second output FET with a source-drain path coupled between the output signal node and a second output supply node.