The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2011
Filed:
Dec. 23, 2009
Gregory W. Alexander, Pflugerville, TX (US);
Fadi Busaba, Poughkeepsie, NY (US);
David A. Schroter, Round Rock, TX (US);
Eric Schwarz, Gardiner, NY (US);
Brian W. Thompto, Austin, TX (US);
Wesley J. Ward, Iii, Pflugerville, TX (US);
Gregory W. Alexander, Pflugerville, TX (US);
Fadi Busaba, Poughkeepsie, NY (US);
David A. Schroter, Round Rock, TX (US);
Eric Schwarz, Gardiner, NY (US);
Brian W. Thompto, Austin, TX (US);
Wesley J. Ward, III, Pflugerville, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.