The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2011
Filed:
Mar. 27, 2007
Jonathan B. Ballagh, Boulder, CO (US);
Michael D. Hirsch, Boulder, CO (US);
Jonathan B. Ballagh, Boulder, CO (US);
Michael D. Hirsch, Boulder, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Methods and systems for simulating an electronic system in a high level modeling system (HLMS). A design block and certain signals of the electronic system are selected. The selected signals include internal signals of the design block that are not ports of the design block. The electronic system is simulated in the HLMS, which includes a hardware-based co-simulation platform and a software-based co-simulation platform. A hardware realization of the design block is automatically generated and the design block is emulated in the hardware based co-simulation platform using the hardware realization of the design block. A sequence of values is displayed for the selected signals of the electronic system. During the simulation of the electronic system in the HLMS, the sequence of values for the internal signals of the design block and another sequence of values for the ports of the design block are transferred between the co-simulation platforms.