Volatile memory elements with minimized area and leakage current

Abstract

Arrays of memory elements may have data lines and address lines. Each memory element may have five transistors. An address decoder may receive an undecoded address signal and may produce a corresponding decoded address signal. The decoded version of the address signal may be used in addressing the memory elements in the memory array. The memory array may be loaded with configuration data. Loaded memory elements may each provide a static output control signal that configures a programmable logic transistor in programmable logic. The memory elements may be powered with an elevated voltage during normal operation. Boosted address signals may be used when addressing the memory array. The address decoder may contain circuitry that is responsive to a clear control signal and an address output enable signal. The memory element array may be cleared by asserting the clear control signal and address output enable signal.