The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
Jan. 30, 2009
Steven Huynh, Fremont, CA (US);
Matthew A. Grant, Palo Alto, CA (US);
Gary M. Hurtz, Pleasanton, CA (US);
David J. Kunst, Cupertino, CA (US);
Trey A. Roessig, Palo Alto, CA (US);
Steven Huynh, Fremont, CA (US);
Matthew A. Grant, Palo Alto, CA (US);
Gary M. Hurtz, Pleasanton, CA (US);
David J. Kunst, Cupertino, CA (US);
Trey A. Roessig, Palo Alto, CA (US);
Active-Semi, Inc., , VG;
Abstract
A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.