The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
Sep. 14, 2009
Stefan G. Block, Munich, DE;
Herbert Preuthen, Dorfen, DE;
Farid Labib, Dieβen, DE;
Stephan Habel, Berg, DE;
Claus Pribbernow, Munich, DE;
Stefan G. Block, Munich, DE;
Herbert Preuthen, Dorfen, DE;
Farid Labib, Dieβen, DE;
Stephan Habel, Berg, DE;
Claus Pribbernow, Munich, DE;
LSI Corporation, Milpitas, CA (US);
Abstract
An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.