The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2011

Filed:

May. 29, 2008
Applicants:

Xiaolin Wang, Concord, MA (US);

Qian Wu, San Jose, CA (US);

Benjamin Marshall, Stow, MA (US);

Fugui Wang, Sterling, MA (US);

KE Ning, Framingham, MA (US);

Gregory Pitarys, Stow, MA (US);

Inventors:

Xiaolin Wang, Concord, MA (US);

Qian Wu, San Jose, CA (US);

Benjamin Marshall, Stow, MA (US);

Fugui Wang, Sterling, MA (US);

Ke Ning, Framingham, MA (US);

Gregory Pitarys, Stow, MA (US);

Assignee:

Axis Semiconductor, Inc., Boxborough, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 15/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.


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