The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
Mar. 10, 2008
Kartik B. Ariyur, Minneapolis, MN (US);
Eric Lautenschlager, Bloomington, MN (US);
Michael R. Elgersma, Plymouth, MN (US);
Kartik B. Ariyur, Minneapolis, MN (US);
Eric Lautenschlager, Bloomington, MN (US);
Michael R. Elgersma, Plymouth, MN (US);
Honeywell International Inc., Morristown, NJ (US);
Abstract
An obstacle-avoidance-processor chip for three-dimensional path planning comprises an analog processing circuit and at least two analog-resistive-grid networks. The analog processing circuit is communicatively coupled to receive data from an inertial measurement unit and from at least one obstacle-detection sensor. The analog processing circuit is configured to construct a three-dimensional obstacle map of an environment based on the received data. The at least two analog-resistive-grid networks are configured to map obstacles in at least two respective non-parallel planes in the constructed three-dimensional obstacle map. The at least two analog-resistive-grid networks form a quasi-three-dimensional representation of the environment. The obstacle-avoidance-processor chip generates information indicative of a three-dimensional unobstructed path in the environment based on the obstacle maps.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile