The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8077602 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 13, 2011

Filed:

Feb. 01, 2008
Applicants:

Lakshminarayana B. Arimilli, Austin, TX (US);

Ravi K. Arimilli, Austin, TX (US);

Bernard C. Drerup, Austin, TX (US);

Jody B. Joyner, Austin, TX (US);

Jerry D. Lewis, Round Rock, TX (US);

Inventors:

Lakshminarayana B. Arimilli, Austin, TX (US);

Ravi K. Arimilli, Austin, TX (US);

Bernard C. Drerup, Austin, TX (US);

Jody B. Joyner, Austin, TX (US);

Jerry D. Lewis, Round Rock, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/08 (2006.01); G06F 11/00 (2006.01); G08C 15/00 (2006.01); H04J 1/16 (2006.01); H04J 3/14 (2006.01); H04L 1/00 (2006.01); H04L 12/26 (2006.01); H04L 12/28 (2006.01); H04L 12/56 (2006.01);
U.S. Cl.
CPC ...
Abstract

Mechanisms for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.


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