The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
Apr. 16, 2008
Yoshimasa Amatatsu, Gunma, JP;
Minoru Akaishi, Gunma, JP;
Satoshi Onai, Gunma, JP;
Katsuya Okabe, Gunma, JP;
Yoshiaki Sano, Tochigi, JP;
Akira Yamane, Gunma, JP;
Yoshimasa Amatatsu, Gunma, JP;
Minoru Akaishi, Gunma, JP;
Satoshi Onai, Gunma, JP;
Katsuya Okabe, Gunma, JP;
Yoshiaki Sano, Tochigi, JP;
Akira Yamane, Gunma, JP;
SANYO Semiconductor Co., Ltd., Gunma, JP;
Semiconductor Components Industries, LLC, Phoenix, AZ (US);
Abstract
A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.