The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
Jul. 20, 2010
Chungho Lee, Sunnyvale, CA (US);
Ashot Melik-martirosian, Sunnyvale, CA (US);
Wei Zheng, Santa Clara, CA (US);
Timothy Thurgate, Sunnyvale, CA (US);
Chi Chang, Saratoga, CA (US);
Hiroyuki Kinoshita, San Jose, CA (US);
Kuo-tung Chang, Saratoga, CA (US);
Unsoon Kim, San Jose, CA (US);
Chungho Lee, Sunnyvale, CA (US);
Ashot Melik-Martirosian, Sunnyvale, CA (US);
Wei Zheng, Santa Clara, CA (US);
Timothy Thurgate, Sunnyvale, CA (US);
Chi Chang, Saratoga, CA (US);
Hiroyuki Kinoshita, San Jose, CA (US);
Kuo-Tung Chang, Saratoga, CA (US);
Unsoon Kim, San Jose, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.