The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2011

Filed:

Aug. 31, 2007
Applicants:

Naoaki Kanagawa, Yokohama, JP;

Kazuaki Kawaguchi, Kawasaki, JP;

Inventors:

Naoaki Kanagawa, Yokohama, JP;

Kazuaki Kawaguchi, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Plural data lines read normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line. Plural parity data lines read parity data from a second area in the memory cell array different from the first area, the parity data being used for an error correction of the normal data stored in the memory cell. A first determination circuit compares the normal data read from the data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. A second determination circuit compares the parity data read from the parity data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. The second determination circuit includes a selection circuit that selectively outputs a determination result on a part of the parity data lines.


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