The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2011

Filed:

Mar. 17, 2008
Applicants:

Masami Kanasugi, Kawasaki, JP;

Koichi Kuroiwa, Kawasaki, JP;

Makoto Muranushi, Kawasaki, JP;

Koji Nozoe, Kawasaki, JP;

Kunimitsu Itashiki, Kawasaki, JP;

Inventors:

Masami Kanasugi, Kawasaki, JP;

Koichi Kuroiwa, Kawasaki, JP;

Makoto Muranushi, Kawasaki, JP;

Koji Nozoe, Kawasaki, JP;

Kunimitsu Itashiki, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/12 (2006.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively.


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