The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2011
Filed:
Feb. 13, 2006
Atsushi Kimata, Kasugai, JP;
Atsushi Kimata, Kasugai, JP;
Fujitsu Semiconductor Limited, Yokohama, JP;
Abstract
A data row of delay time ratio coefficient (hereinafter referred to as DMAG value) is selected from a delay information library (D) (S) for every circuit cell in a use condition range of a logic circuit, and the minimum value or/and maximum value of a DMAG value is extracted (S). The minimum value or/and the maximum delay time is/are calculated for every circuit cell by multiplying the standard delay time to the extracted DMAG value (S). The above processing is performed for all the circuit cells constituting the logic circuit ((S): NO), and the data set of the minimum or/and maximum delay time in the use condition range of the logic circuit is/are acquired for every circuit cell (S). When the delay time characteristic of the circuit cell is nonlinear, the delay time serving as the minimum or/and the maximum for every circuit cell can be freely selected in the range of the circuit use condition unlike the case where the delay time is calculated by uniformly assigning the same use condition to all circuit cells.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile