The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2011
Filed:
Sep. 14, 2007
Anne S. Verhulst, Houtvenne, BE;
William G. Vandenberghe, Heverlee, BE;
Anne S. Verhulst, Houtvenne, BE;
William G. Vandenberghe, Heverlee, BE;
IMEC, Leuven, BE;
Katholieke Universiteit Leuven, K.U. Leuven R&D, Leuven, BE;
Abstract
Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these elongate monocrystalline nanostructure Si/Ge TFETs resulting in ultra-high on-chip transistor densities.