Error correction circuit and method, and semiconductor memory device including the circuit

Abstract

An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type. The semiconductor memory device includes the error correction circuit, an error checking and correcting (ECC) encoder generating syndrome data based on information data and generating the coded data by combining the syndrome data with information data, and a memory core storing the coded data. Multi-bit ECC performance is maintained and ECC for a predetermined (1 or 2) or less number of error bits is quickly performed.