Cache memory

Abstract

Disclosed is a cache memory, and more particularly to a cache memory, in which a word-line voltage control logic unit and a word-line driver are added as a logic circuit between a row decoder and a word line, so that a reinforcement voltage signal having a higher level than a basic voltage signal can be applied when accessing the word line corresponding to an access time failure, thereby decreasing an access time delay in the word line in order to minimize an access failure to the cache memory due to process variation. The cache memory including: a row decoder which decodes and outputs an input address signal; a plurality of word-line voltage control logic units which output a basic voltage signal or a reinforcement voltage signal having a higher voltage level than the basic voltage signal according to whether or not word lines involve a cell having an access time failure; and word-line drivers which are one-to-one connected to output lines of the row decoder and supply the word lines with the basic voltage signal or the reinforcement voltage signal output from the word-line voltage control logic unit only if a signal output through the output line of the row decoder is an activation signal.