The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2011
Filed:
Jun. 23, 2008
Leeshawn Luo, San Jose, CA (US);
Anup Bhalla, Santa Clara, CA (US);
Yueh-se Ho, Sunnyvale, CA (US);
Sik K. Lui, Sunnyvale, CA (US);
Mike Chang, Cupertino, CA (US);
Leeshawn Luo, San Jose, CA (US);
Anup Bhalla, Santa Clara, CA (US);
Yueh-Se Ho, Sunnyvale, CA (US);
Sik K. Lui, Sunnyvale, CA (US);
Mike Chang, Cupertino, CA (US);
Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);
Abstract
A semiconductor integrated circuit package having a leadframe () that includes a leadframe pad () disposed under a die () and a bonding metal area () that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area () increases the number of interconnections between the metal area () and the die () to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body () is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101) is used for the source terminal (). The bonding metal area may have a 'L' shape, a 'C' shape, a “J” shape, an “I” shape or any combination thereof.