The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2011
Filed:
Sep. 07, 2005
Michael Priel, Hertzlia, IL;
Dan Kuzmin, Givat Shmuel, IL;
Anton Rozen, Gedera, IL;
Eitan Zmora, Jerusalem, IL;
Michael Priel, Hertzlia, IL;
Dan Kuzmin, Givat Shmuel, IL;
Anton Rozen, Gedera, IL;
Eitan Zmora, Jerusalem, IL;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.