The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8065634 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 22, 2011

Filed:

Sep. 29, 2008
Applicants:

Nishant Patil, Mountain View, CA (US);

Subhasish Mitra, Palo Alto, CA (US);

Inventors:

Nishant Patil, Mountain View, CA (US);

Subhasish Mitra, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for validating a nanotube logic network. The nanotube logic network is separated into regions based on a conductivity of the respective region. Potential paths through adjoining regions of the nanotube logic network are determined. Boolean path functions for each potential path are determined. If the Boolean path functions of the potential paths are equivalent to the intended logic function, then the nanotube logic network is immune to misaligned carbon nanotubes.


Find Patent Forward Citations

Patil, Nishant. (2011). System and method for analyzing a nanotube logic circuit (U.S. Patent No. 8065634). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8065634

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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