The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2011
Filed:
Jun. 30, 2009
Thomas A. Ziaja, Austin, TX (US);
Murali Gala, San Jose, CA (US);
Paul J. Dickinson, San Jose, CA (US);
Karl P. Dahlgren, Evemont, CA (US);
David L. Curwen, Mountain View, CA (US);
Oliver Caty, Sunnyvale, CA (US);
Steven C. Krow-lucal, Sunnyvale, CA (US);
James C. Hunt, Redwood City, CA (US);
Poh-joo Tan, San Jose, CA (US);
Thomas A. Ziaja, Austin, TX (US);
Murali Gala, San Jose, CA (US);
Paul J. Dickinson, San Jose, CA (US);
Karl P. Dahlgren, Evemont, CA (US);
David L. Curwen, Mountain View, CA (US);
Oliver Caty, Sunnyvale, CA (US);
Steven C. Krow-Lucal, Sunnyvale, CA (US);
James C. Hunt, Redwood City, CA (US);
Poh-Joo Tan, San Jose, CA (US);
Oracle America, Inc., Redwood City, CA (US);
Abstract
An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.