Clock generation circuit, recording device and clock generation method

Abstract

A clock generation circuit is provided that multiplies an input signal of a specific frequency by a specific multiplication factor and generates an output clock signal. The clock generation circuit includes a PLL circuit that multiplies the input signal and generates the output clock signal, and a correction circuit that changes the multiplication factor of the PLL circuit. The correction circuit changes the PLL circuit multiplication factor by increasing or decreasing the specific multiplication factor, the change being performed only during a correction interval for each correction cycle, the correction cycle being longer than one cycle of the input signal, and being performed such that a time difference between an input synchronizing signal synchronized with the input signal and an output synchronizing signal synchronized with the output clock signal is reduced. The PLL circuit multiplies the input signal by the changed multiplication factor during the correction interval.