The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2011

Filed:

Nov. 08, 2007
Applicant:

Tetsuo Kamada, Kanagawa-ken, JP;

Inventor:

Tetsuo Kamada, Kanagawa-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit includes a clock generator and a synchronous clock circuit unit. The clock generator generates a first clock signal, a second clock signal, and a third clock signal, which are synchronized with one another and are provided with mutually different frequencies. The synchronous clock circuit unit includes synchronous clock circuits to which the first clock signal, the second clock signal, and the third clock signal are inputted, respectively. The synchronous clock circuits are scanned by use of the first clock signal, the second clock signal, and the third clock signal.


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Kamada, Tetsuo. (2011). Scan-based integrated circuit having clock frequency divider (U.S. Patent No. 8065549). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8065549

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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