The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2011

Filed:

Aug. 22, 2006
Applicants:

Ata Khan, Saratoga, CA (US);

Greg Goodhue, San Jose, CA (US);

Pankaj Shrivastava, San Jose, CA (US);

Bas Van Der Veer, Fiddletown, CA (US);

Rick Varney, Campbell, CA (US);

Prithvi Nagaraj, Sunnyvale, CA (US);

Inventors:

Ata Khan, Saratoga, CA (US);

Greg Goodhue, San Jose, CA (US);

Pankaj Shrivastava, San Jose, CA (US);

Bas Van Der Veer, Fiddletown, CA (US);

Rick Varney, Campbell, CA (US);

Prithvi Nagaraj, Sunnyvale, CA (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 17/50 (2006.01); G06F 9/445 (2006.01); G06F 12/00 (2006.01); G06F 9/44 (2006.01); G06F 7/04 (2006.01); G06F 11/00 (2006.01); G01R 27/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

One embodiment of the present application includes a microcontroller () that has an embedded memory (), a programmable processor (), and a test interface (). The memory () is accessible through the test interface (). In response to resetting this microcontroller (), a counter is started and the test interface () is initially set to a disabled state while an initiation program is executed. The test interface () is changed to an enabled state—such that access to the embedded memory () is permitted through it—when the counter reaches a predefined value unless the microcontroller () executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller () operation.


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