Equalization circuitry including a digital-to-analog converter having a voltage divider and a multiplexer

Abstract

An equalization circuitry that includes a digital-to-analog converter having a voltage divider and a multiplexer coupled to the voltage divider is described. In one implementation, the digital-to-analog converter provides a control signal to a plurality of single-stage equalizer control logic circuits. Also, in one implementation, the multiplexer receives a plurality of inputs from the voltage divider and selects an output from the plurality of inputs. Furthermore, in one implementation, the voltage divider includes a plurality of resistors coupled in series. Also, in one implementation, the voltage divider further includes a first resistor coupled to the plurality of resistors, ground, and a lowest voltage input terminal of the multiplexer, where a voltage across the first resistor is an input voltage to the lowest voltage input terminal. Additionally, in one implementation, the voltage divider further includes a second resistor coupled to the plurality of resistors and a supply voltage, where the supply voltage minus a voltage across the second resistor and a voltage across a resistor of the plurality of resistors is an input voltage to a highest voltage input terminal of the multiplexer. In one implementation, the first and second resistors are programmable in user mode.