The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2011
Filed:
Aug. 08, 2010
Kapil Narula, Faridkot, IN;
Amol Agarwal, Noida, IN;
Sumeet Aggarwal, Delhi, IN;
Sunit K. Bansal, Ghaziabad, IN;
Sabaa Sandhu, Amritsar, IN;
Harkaran Singh, Noida, IN;
Kapil Narula, Faridkot, IN;
Amol Agarwal, Noida, IN;
Sumeet Aggarwal, Delhi, IN;
Sunit K. Bansal, Ghaziabad, IN;
Sabaa Sandhu, Amritsar, IN;
Harkaran Singh, Noida, IN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic states in response to an inactive edge of the clock signal, and selectively changes the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, such that the selection depends on the logic state of the data input. The pulse generator circuit enables the pulse input signal in response to an active edge of the clock signal, and disables the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node. The latch stores a data output signal for output at the data output, the data output signal depending on the logic state of the third node.