The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2011

Filed:

Jan. 28, 2010
Applicants:

Thomas H. Strader, San Jose, CA (US);

Roger D. Flateau, Jr., Albuquerque, NM (US);

Schuyler E. Shimanek, Albuquerque, NM (US);

Wayne E. Wennekamp, Rio Rancho, NM (US);

Adam Elkins, Rio Rancho, NM (US);

Inventors:

Thomas H. Strader, San Jose, CA (US);

Roger D. Flateau, Jr., Albuquerque, NM (US);

Schuyler E. Shimanek, Albuquerque, NM (US);

Wayne E. Wennekamp, Rio Rancho, NM (US);

Adam Elkins, Rio Rancho, NM (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.


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