The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2011
Filed:
Jul. 10, 2006
Helmut Puchner, Santa Clara, CA (US);
Oliver Pohland, San Jose, CA (US);
Helmut Puchner, Santa Clara, CA (US);
Oliver Pohland, San Jose, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A regulated circuit having a number of metal-oxide-semiconductor field effect transistors (MOS FETs) and a method for using the same are provided to reduce Negative Bias Temperature Instability degradation of the MOS FETs on the circuit. In one embodiment, the method involves steps of: (i) detecting degradation in performance of at least one of the MOS FETs causing a shift in threshold voltage (V) of the MOS FET; and (ii) if the shift in Vexceeds a predetermined value, forward biasing the MOS FETs, thereby reducing or reversing the shift in V. Optionally, the method includes an initial step of determining if the circuit is in a non-dynamic operating mode before forward biasing the MOS FETs. Other embodiments are also disclosed.