The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2011

Filed:

Sep. 19, 2007
Applicants:

Lars-erik Wernersson, Lund, SE;

Erik Lind, Malmö, SE;

Tomas Bryllert, Göteborg, SE;

Jonas Ohlsson, Malmö, SE;

Truls Löwgren, Malmö, SE;

Lars Samuelson, Malmö, SE;

Claes Thelander, Lund, SE;

Inventors:

Lars-Erik Wernersson, Lund, SE;

Erik Lind, Malmö, SE;

Tomas Bryllert, Göteborg, SE;

Jonas Ohlsson, Malmö, SE;

Truls Löwgren, Malmö, SE;

Lars Samuelson, Malmö, SE;

Claes Thelander, Lund, SE;

Assignee:

QuNano AB, Lund, SE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.


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