The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2011
Filed:
Apr. 16, 2009
Paul W. Sanders, Scottsdale, AZ (US);
Michael F. Petras, Phoenix, AZ (US);
Chandrasekaram Ramiah, Phoenix, AZ (US);
Paul W. Sanders, Scottsdale, AZ (US);
Michael F. Petras, Phoenix, AZ (US);
Chandrasekaram Ramiah, Phoenix, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region () of a first thickness () proximate the front surface () of a substrate wafer () by: (i) from the front surface (), forming comparatively shallow vias () of a first aspect ratio containing first conductors () extending preferably through the first thickness () but not through the initial wafer () thickness (), (ii) removing material (″) from the rear surface () to form a modified wafer () of smaller final thickness () with a new rear surface (), and (iii) forming from the new rear surface (), much deeper vias () of second aspect ratios beneath the device region () with second conductors () therein contacting the first conductors (), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.