The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2011

Filed:

Dec. 23, 2009
Applicants:

Hyun-sik Seo, Anyang-si, KR;

Jong-uk Bae, Seoul, KR;

Dae-hwan Kim, Gumi-si, KR;

Inventors:

Hyun-Sik Seo, Anyang-si, KR;

Jong-Uk Bae, Seoul, KR;

Dae-Hwan Kim, Gumi-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating an array substrate for a display device includes steps of forming a gate line and a gate electrode on a substrate, forming a gate insulating layer and an intrinsic amorphous silicon layer, forming an oxide semiconductor layer, increasing a conductive property of the oxide semiconductor layer, forming a metal layer, forming a first photoresist pattern and a second photoresist pattern having a thinner thickness than the first photoresist pattern, forming a data line, a source drain pattern, an oxide semiconductor pattern and an active layer, removing the second photoresist pattern and exposing the source drain pattern, wet-etching the source drain pattern using a first etchant, thereby forming source and drain electrodes, wet-etching the oxide semiconductor pattern using a second etchant, thereby forming ohmic contact layers, removing the first photoresist pattern, forming a passivation layer having a drain contact hole exposing the drain electrode on the source and drain electrodes, and forming a pixel electrode connected to the drain electrode through the drain contact hole, wherein the active layer has a uniform thickness in the switching region.


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