Digital device interconnect system

Abstract

A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.