The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
Jun. 15, 2010
Dennis C. Ferguson, Palo Alto, CA (US);
Philippe Lacroute, Sunnyvale, CA (US);
Chi-chung Chen, Cupertino, CA (US);
Gerald Cheung, Palo Alto, CA (US);
Tatao Chuang, San Jose, CA (US);
Pankaj Patel, Cupertino, CA (US);
Viswesh Anathakrishnan, Sunnyvale, CA (US);
Dennis C. Ferguson, Palo Alto, CA (US);
Philippe Lacroute, Sunnyvale, CA (US);
Chi-Chung Chen, Cupertino, CA (US);
Gerald Cheung, Palo Alto, CA (US);
Tatao Chuang, San Jose, CA (US);
Pankaj Patel, Cupertino, CA (US);
Viswesh Anathakrishnan, Sunnyvale, CA (US);
Juniper Networks, Inc., Sunnyvale, CA (US);
Abstract
Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of 'virtual queues' corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.