The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
Jun. 16, 2010
Michael T. Niemier, Granger, IN (US);
Mohammad T. Alam, Berkeley, CA (US);
Gary H. Bernstein, Granger, IN (US);
Xiaobo Sharon HU, Granger, IN (US);
Wolfgang Porod, Granger, IN (US);
Edit Varga, Gyula, HU;
Michael T. Niemier, Granger, IN (US);
Mohammad T. Alam, Berkeley, CA (US);
Gary H. Bernstein, Granger, IN (US);
Xiaobo Sharon Hu, Granger, IN (US);
Wolfgang Porod, Granger, IN (US);
Edit Varga, Gyula, HU;
The University of Notre Dame Du Lac, Notre Dame, IN (US);
Abstract
A non-majority magnetic logic gate device for use in constructing compact and power efficient logical magnetic arrays is presented. The non-majority magnetic logic gate device includes a substrate, symmetrically aligned magnetic islands (SAMIs), at least one misaligned magnetic island (MAMI), magnetic field inputs (MFIs), and at least one magnetic field output (MFO). The SAMIs and MAMI are electrically isolated from each other but are magnetically coupled to one another through their respective magnetic fringe fields. The MAMI is geometrically and/or angularly configured to exhibit a magnetization ground state bias which is dependent upon which direction the applied magnetic clock field is swept. Non-majority logic gates can be made from layouts containing the SAMIs and the MAMI which contain a smaller number of components as comparable majority logic gate layouts.