The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2011

Filed:

Jun. 30, 2008
Applicants:

Deok-kee Kim, Seoul, KR;

Yoon-dong Park, Yongin-si, KR;

Seung-hoon Lee, Seoul, KR;

I-hun Song, Seongnam-si, KR;

Won-joo Kim, Hwaseong-si, KR;

Young-gu Jin, Hwaseong-si, KR;

Hyuk-soon Choi, Seongnam-si, KR;

Suk-pil Kim, Yongin-si, KR;

Inventors:

Deok-kee Kim, Seoul, KR;

Yoon-dong Park, Yongin-si, KR;

Seung-hoon Lee, Seoul, KR;

I-hun Song, Seongnam-si, KR;

Won-joo Kim, Hwaseong-si, KR;

Young-gu Jin, Hwaseong-si, KR;

Hyuk-soon Choi, Seongnam-si, KR;

Suk-pil Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.


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