The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
Oct. 07, 2009
Derek Hullinger, Orem, UT (US);
Keith Decker, Pleasant Grove, UT (US);
Derek Hullinger, Orem, UT (US);
Keith Decker, Pleasant Grove, UT (US);
Moxtek, Inc., Orem, UT (US);
Abstract
A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile