The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
Jun. 29, 2009
Chu-feng Chen, Taipei County, TW;
Chung-ren Lao, Taichung County, TW;
Pai-chun Kuo, Hsinchu County, TW;
Chien-hsien Song, Kaohsiung, TW;
Hua-chun Chiue, Taichung, TW;
An-hung Lin, Taipei County, TW;
Chu-Feng Chen, Taipei County, TW;
Chung-Ren Lao, Taichung County, TW;
Pai-Chun Kuo, Hsinchu County, TW;
Chien-Hsien Song, Kaohsiung, TW;
Hua-Chun Chiue, Taichung, TW;
An-Hung Lin, Taipei County, TW;
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Abstract
A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.