The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
May. 02, 2008
Michael Hecker, Reichenberg, DE;
Ehrenfried Zschech, Moritzburg, DE;
Piotr Grabiec, Osowiec, PL;
Pawel Janus, Brwinów, PL;
Teodor Gotszalk, Wroclaw, PL;
Michael Hecker, Reichenberg, DE;
Ehrenfried Zschech, Moritzburg, DE;
Piotr Grabiec, Osowiec, PL;
Pawel Janus, Brwinów, PL;
Teodor Gotszalk, Wroclaw, PL;
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
By forming an appropriate material layer, such as a metal-containing material, on a appropriate substrate and patterning the material layer to obtain a cantilever portion and a tip portion, a specifically designed nano-probe may be provided. In some illustrative aspects, additionally, a three-dimensional template structure may be provided prior to the deposition of the probe material, thereby enabling the definition of sophisticated tip portions on the basis of lithography, wherein, alternatively or additionally, other material removal processes with high spatial resolution, such as FIB techniques, may be used for defining nano-probes, which may be used for electric interaction, highly resolved temperature measurements and the like. Thus, sophisticated measurement techniques may be established for advanced thermal scanning, strain measurement techniques and the like, in which a thermal and/or electrical interaction with the surface under consideration is required. These techniques may be advantageously used for failure localization and local analysis during the fabrication of advanced integrated circuits.