The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2011
Filed:
May. 21, 2008
Toshiyuki Maeda, Kanagawa, JP;
Toshiharu Asaka, Kanagawa, JP;
Toshiyuki Maeda, Kanagawa, JP;
Toshiharu Asaka, Kanagawa, JP;
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Abstract
A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.